1. Field of the Invention
The present invention relates to a display device structured by a pixel portion that uses light emitting elements such as liquid crystal elements or electroluminescence elements (EL elements), and to electronic equipment using the display device in a display portion. In particular, the present invention relates to a display device having a pixel portion and a driver circuit for driving the pixel portion formed on the same insulating surface, and to electronic equipment using the display device in a display portion.
2. Description of the Related Art
In recent years, display devices in which semiconductor thin films are formed on an insulating surface such as a glass substrate, in particular electronic circuits using thin film transistors (hereinafter referred to as TFTs), are in use in all fields. In particular, their use in display devices is common, and active matrix display devices such as LCDs (liquid crystal displays) are utilized in many products and widely adopted. Active matrix display devices using TFTs have several hundred thousand to several million pixels arranged in a matrix shape, and image display is performed by controlling the electric charge of each pixel by using TFTs disposed in each pixel.
Recently, techniques relating to polysilicon TFTs have progressed, which are used for simultaneously forming driver circuits on the same substrate by using TFTs in regions that are in the periphery of a pixel portion in addition to pixel TFTs that structure pixels. These techniques contribute greatly to making devices smaller and reducing their electric power consumption. Display devices have thus become indispensable devices used in display portions and the like on mobile information terminals, whose expanded fields of application have become remarkable in recent years.
An example of a general display device is shown in FIG. 2A. FIG. 2A is an example of a liquid crystal display device in which a pixel portion and a driver circuit are integrally formed on an insulating surface. A pixel portion 201 is disposed in a center portion on a substrate 200, and a source signal line driver circuit 202, gate signal line driver circuits 203, and the like are formed in the periphery of the pixel portion 201. Note that although the gate signal line driver circuits 203 are disposed symmetrically on both right and left sides of the pixel portion 201 in FIG. 2A, they may also be placed on only one side. However, it is preferable to arrange the gate signal line driver circuits symmetrically as in FIG. 2A when considering the reliability of circuit operation, efficiency, and the like.
Signals input to the source signal line driver circuit 202 and the gate signal line driver circuits 203 are supplied form the outside through a flexible printed circuit (FPC) 204.
An opposing electrode and the like are formed in an opposing substrate 210, and the opposing substrate 210 and the substrate 200 are bonded through a sealing agent 205 while maintaining a certain gap. A liquid crystal material is then injected into the gap between the substrate 200 and the opposing substrate 210 from an injection port prepared in advance. The injection port is then sealed tightly by using a sealant 206.
m source signal lines and n gate signal lines are disposed orthogonally in the pixel portion 201 as shown in FIG. 2B. There are m source signal lines and n gate signal lines in FIG. 2B. Locations 220 at which the source signal lines and the gate signal lines intersect form pixels as shown in FIG. 2C. The pixel comprises a source signal line 221, a gate signal line 222, a pixel TFT 223, a liquid crystal element 224, a storage capacitor 225, and an opposing electrode 226. The number of pixels here is m×n pixels.
Operation of the display device is explained simply with reference to FIGS. 5A to 5C. In general, screen drawing is performed on the order of 60 times per second so that pixel flicker is not recognizable by human eyes. A period denoted by reference numeral 501, that is, a period necessary to draw the screen one time, is referred to as one frame period here (see FIG. 5A).
Selection of the gate signal lines is performed in sequence from a first row in one frame period. A selection period 504 per one row is denoted as a horizontal period. A period 502 up until selection of the final row (number n row) is complete is denoted as a line scanning period. Similar operations are then performed in the next frame period, sandwiching a vertical return period 503 (see FIG. 5B).
Write-in of the image signal in sequence to the pixels of the selected row is performed in one horizontal period from the source signal lines. This period, a period 505, is denoted as a dot sampling period. A period 507 necessary for writing in an image signal to one pixel is denoted as one dot sampling period. When write-in of the image signal in one row portion of pixels is complete, similar operations are performed in the next horizontal period, sandwiching a horizontal return period 506 (see FIG. 5C).
Specific circuit operation is explained next. FIG. 6A is an example of the structure of the source signal line driver circuit of the display device, and has a shift register 602 that uses a plurality of stages of flip-flops (FFs) 601, a NAND 603, a buffer 604, and a sampling switch 605. Operation is explained with reference to FIG. 6B. The shift register 602 outputs pulses in order from the first stage in accordance with a clock signal (CK), a clock inverted signal (CKb), and a start pulse (SP).
In the case where the pulses output from the shift register 602 overlap in adjacent stages, they are input to the NAND 603 and pulses that do not overlap in adjacent stages are formed. The NAND output then passes through the buffer 604, and becomes sampling pulses.
When the sampling pulses are input to the sampling switch 605, the sampling switch 605 is turned on, and the electric potential of an image signal (Video) charges the source signal line connected to the sampling switch during that period. At the same time, the image signal is written into one pixel connected to the source signal line of the row whose gate signal line is selected. In FIG. 6B, a period denoted by reference numeral 610 is one dot sampling period.
A gate signal line driver circuit shown in FIG. 7A is explained next. The structure from a shift register to a buffer is nearly the same as that of the source signal line driver circuit, and the gate signal line driver circuit has a shift register 702 that comprises a plurality of stages of flip-flops 701, a NAND 703, and a buffer 704.
Operation is explained with reference to FIG. 7B. Similarly to the source signal line driver circuit, the shift register 702 outputs pulses in order from the first stage in accordance with the clock signal (CK), the clock inverted signal (CKb), and the start pulse (SP).
In the case where the pulses output from the shift register 702 overlap in adjacent stages, they are input to the NAND 703 and pulses that do not overlap in adjacent stages are formed. The NAND output then passes through the buffer 704, and becomes gate signal line selection pulses.
As stated above, the image signal written into the source signal line is then written into each of the pixels in the row to which a gate signal line selection pulse is input. In FIG. 7B, a period denoted by reference numeral 710 is one horizontal period, and a period denoted by reference numeral 720 is the one dot sampling period mentioned above.
In the case where the display device has many functions, such as with a personal computer, the display device may be used in a horizontal format for certain applications, and in a vertical format in other applications. For cases such as this, there is a method of displaying in a state in which a display device frame is rotated by 90°, as shown in FIG. 3A.
A pixel portion of an active matrix display device has m×n pixels arranged in a matrix shape as shown in FIG. 2B. Write-in of an image signal is performed in sequence from a pixel at coordinate (1,1), followed by (1,2), (1,3), and (1,4). One horizontal period is complete when (1,m) is reached. This is repeated n times, and write-in of one screen is complete when write-in is performed to the final pixel at coordinate (m,n).
Once again return to FIG. 3A. In the case of horizontal format display (left side) and vertical format display (right side), the pixels at coordinate (1,1) into which write-in is performed first are denoted by reference numerals 301 and 302, respectively. Considering cases of performing display of similar images in horizontal format display and vertical format display, the input order is in sequence from the upper left to the upper right, and on downward to the lower right when the image signal input corresponds to horizontal format display, as shown in FIG. 3A. In the case of performing vertical format display using this image signal, the write-in order to the display device itself does not change, and therefore the sequence for inputting the image signal must be from the upper right to the lower right, and then leftward toward the lower left.
However, it is preferable to be able to perform switch over to horizontal format display flexibly with the display device, and therefore the preparation of image signal having different formats is not efficient. Display is then performed using a frame memory, storing the image signal temporarily in the memory and then reading it out.
A frame memory is for storing the image signal of each pixel in respective memory cells, and it is therefore possible to read out from arbitrary addresses, irrespective of the write-in order. By changing the readout order of the image signal written temporarily into the frame memory, switch over between vertical and horizontal display can be performed.
The frame memory for storing one frame portion of an image signal has memory circuits managed by addresses, as shown in FIG. 3B. When the image signal is input, it is therefore written in sequence into the addresses (1,1), (2,1), . . . , (m,1), (1,2), (2,2), . . . , (m,2), (1,n), (2,n), . . . , and (m,n). For horizontal format display, readout is performed in the same sequence as the write-in.
On the other hand, for vertical format display, readout is performed in sequence from the addresses (m,1), (m,2), . . . , (m,n), (m−1,1), (m−2,2), . . . , (m−1,n), . . . , (1,1), (1,2), . . . , and (1,n), when display as in FIG. 3A is desired.
Further, the frame memory generally has at least two frame portions formed, as shown in FIG. 4A. During a period in which write-in to one of the frame memories is performed, readout from the other frame memory is performed, thus performing display.
The display device can thus perform switch over between vertical and horizontal screens by using normal drive as is. However, the number of pixels in the horizontal and vertical directions of the display device is normally different, and therefore it is necessary to change the format of the image signal at the same time as performing switch over between vertical and horizontal displays.
The image signal is structured by a total of n row portions of image signals: an image signal to be written into the pixels 1 to m of the number 1 row, an image signal to be written into the pixels 1 to m of the number 2 row, . . . , an image signal to be written into the pixels of the number n row, as shown in FIG. 4B(i). In this case, the signal corresponds to m(side)×n(length) pixels. To perform switch over between horizontal and vertical display, it is necessary to convert to a shape corresponding to −n columns of pixels horizontally by m rows of pixels vertically, as shown in FIG. 4B(ii). This operation is referred to as format conversion. Known techniques may be used for the format conversion process itself, and therefore the details are omitted here.
For instance, in case of m(side)×n(length) pixels, an image signal corresponding to one frame period is formed by gathering image signals of n lines, each image signal corresponding to one dot sampling period×m dots. When length and side of the screen change places, it becomes a display region of n(side)×m(length) pixels. The image signal for one frame period need to reconstitute so as to be an image signal corresponding to one frame period that is formed by gathering image signals of m lines, each image signal corresponding to one dot sampling period×n dots.
Here, horizontal element changes from m dots to n dots. When one dot sampling period is the same, the length of one horizontal period becomes n/m. image signal corresponding to one horizontal period is reconstituted by expanding or shortened the image signal corresponding to one horizontal period to suit the n/m length of one horizontal period and sampling of n dots.
On the other hand, it is not possible to correspond by the change in the sampling frequency because the number of lines increase and decrease to the element of the vertical direction. Therefore, it is done by increasing the number of lines a frame by thinning out a part of image signal and decreasing the number of lines a frame, and inputting a part of image signal oppositely two or more lines (For instance, two lines are continued) more than once.
Such a function is offered with IC chip installed beforehand outside, and the converted resolution has been decided to several kinds beforehand but usually;
The method of doing the format conversion high-quality and efficiently is indicated in open 2001-246939 special titles etc., and you may use such a technique.
Various types of software are recently being supplied even to small size portable terminals such as mobile phones, and there is a tendency for one unit to have more and more uses. A vertical and horizontal display switch over technique such as one described above therefore becomes very important.
However, a frame memory is prepared as externally mounted, separate from the display device. That is, the number of component parts increases. In particular, compact portable terminals have grown increasingly smaller recently, and therefore it is difficult to add an additional externally mounted frame memory to present day size terminals. Performing switch over between horizontal and vertical display by a conventional method is therefore not preferable for small size portable terminals.